`include "define.svh"

module ctrl(
    input wire                          div_stall_request,
    input wire                          load_use_stall_request,
    input wire                          inst_stall_request,
    input wire                          data_stall_request,
    
    output reg                          if_stage_stall,
    output reg                          id_stage_stall,
    output reg                          ex_stage_stall,
    output reg                          mem_stage_stall,
    output reg                          wb_stage_stall
);

    reg [4 : 0]                 div_reg;
    reg [4 : 0]                 load_use_reg;
    reg [4 : 0]                 inst_reg;
    reg [4 : 0]                 data_reg;
    
    always_comb begin
        div_reg      = {5{div_stall_request}};
        load_use_reg = {3'b000, {2{load_use_stall_request}}};
        inst_reg     = {5{inst_stall_request}};
        data_reg     = {5{data_stall_request}};
    end
    
    always_comb begin
        if_stage_stall  = div_reg[0] | load_use_reg[0] | inst_reg[0] | data_reg[0];
        id_stage_stall  = div_reg[1] | load_use_reg[1] | inst_reg[1] | data_reg[1];
        ex_stage_stall  = div_reg[2] | load_use_reg[2] | inst_reg[2] | data_reg[2];
        mem_stage_stall = div_reg[3] | load_use_reg[3] | inst_reg[3] | data_reg[3];
        wb_stage_stall  = div_reg[4] | load_use_reg[4] | inst_reg[4] | data_reg[4];
    end
    
    
endmodule
